Modeling of Inner Fringing Charges and Short Channel Effects in Negative Capacitance MFIS Transistor

We propose a compact model for bias dependent inner fringing (IF) charges and the short channel effects (SCEs) for the Metal-Ferroelectric-Insulator-Semiconductor Double Gate Negative Capacitance Field Effect Transistor (MFIS DG-NCFET) using a novel capacitor network approach. We extensively validate the unconventional SCEs stemming from inner fringing field lines including threshold voltage roll-up (V_th roll-up), negative drain induced barrier lowering (NDIBL), and steep sub-threshold swing (SS) for the sub-threshold region using TCAD results. The proposed model is implemented in Verilog-A, which captures the SCEs for different channel lengths through a single set of parameters.