Suppression of threshold voltage shift on In-Si-O-C Thin-Film Transistor with an Al2O3 Passivation Layer under Negative and Positive Gate-Bias Stress

We investigated effect of an Al₂O₃ passivation layer on threshold voltage shift (ΔV_th) of Al₂O₃ insulator/In-Si-O-C thin-film transistors (TFTs) under several gate bias stress conditions. A large ΔV_th due to the four components such as electron trap, hole trap at around the valence band edge, deep trap, and generated hole was observed in In-Si-O-C TFT. By introducing an Al₂O₃ passivation layer, ΔV_th due to the deep trap and generated hole could be reduced 37%.