An Approach for Optimizing Yield of Embedded Memories on Mobile SoC Chips

In this paper, we present an approach to optimizing the yield of embedded static random access memories (SRAM) on mobile SoC chips. This methodology is based on new and ongoing developments in design approach, test methods, diagnosis, and data analysis which has been improved over several process nodes and fully integrated for our 7nm SoC and modem chips. In preparation for future nodes, we are developing methodologies to improve resolution of our fast diagnosis methodologies so that we can collect failing bit information during Wafer Sort and Final Test. We are also researching methods to isolate fault in logic periphery circuits to eliminate or minimize the need for electrical failure analysis such as Photoemission Electron Microscopy and Dynamic Laser Stimulation which are time and resource intensive. This paper concludes by sharing the status and promise of these ongoing developments.