Exploring Adaptive Cache for Reconfigurable VLIW Processor

In this paper, we focus on a very long instruction word (VLIW) processor design that “shares” its cache blocks when switching to different performance modes to alleviate the aforementioned cold starts. The switching trigger cache resizing operations and improper use can lead to less efficient cache performance. We clearly note here that our investigation pertains the local temporal effects of the cache resizing and how we counteract the negative impact of cache misses in such resizing instances. We propose a novel reconfigurable d-cache framework that can dynamically adapt its least recently used (LRU) replacement policy without much hardware overhead. We demonstrate that using our adaptive d-cache, it ensures a smooth cache performance from one cache size to the other. This approach is orthogonal to future research in cache resizing for such architectures that take into account energy consumption and performance of the overall application. Our results show that when compared with a straightforward cache resizing approach, we can achieve a reduction of 10%-63% of cache misses during the switching period. Furthermore, we can also increase the average cache hit rate from 56% to 90% in the cache part that remains live after downsizing using our approach.