Implementation of Folded FIR filter based on Pipelined Multiplier Array

The Finite Impulse response (FIR) filter in direct and transposed form based on pipelined multiplier array is introduced. The proposed scheme is the folded FIR filter based on pipelined carry-save and carry-propagate multipliers. Initially, the Multiplier-accumulator is pipelined at the bit-level based on carry-save and carry-propagate multiplier and then folded the FIR structure, which can avoid the clock skew problem in synchronous circuit. Folding also reduces the hardware complexity. But it has the disadvantage of reducing the sample rate even though it reduces the hardware complexity. Pipelining of the folded FIR structures in direct and transposed form FIR filter increases the throughput of the filter. Verilog and Xilinx implementation of folded array FIR filter design based on pipelined carry propagate multiplier and pipelined carry save multiplier, in both direct and transposed form has been carried out in this work. These proposed schemes are then compared with each other based on the complexity of hardware. The most efficient design among the proposed designs can be selected on the basis of the hardware complexity.