Modeling of Hysteretic Jump Points in Ferroelectric MOS Capacitors

Negative capacitance devices generally exhibit hysteresis, which can be exploited for memory but should be suppressed for logic devices. The significant nonlinearity of ferroelectric (FE) metal–oxide–semiconductor (MOS) capacitor makes it difficult to manipulate hysteresis, especially when multiple material and device parameters are considered simultaneously. Here we model hysteretic jump points (HJPs) and describe how hysteresis responds to different parameters used. First, the energy landscape of FE-MOS capacitor is explored based on the Gibbs free energy, considering forward and backward sweep of gate voltage, to identify the HJPs. Our simulation shows that the surface potential of HJP has a logarithmic relation to the doping concentration of the semiconductor while FE thickness ( ${T}_{\text {FE}}$ ) and gate oxide thickness (EOT) shift the value of the surface potential up or down. Based on the developed model, we introduce hysteresis width and height to evaluate the extent of hysteresis and the amplification of potential quantitatively. Our results show that hysteresis width is a strong function of EOT and ${T}_{\text {FE}}$ but the potential amplification is limited, especially when EOT is thin. In addition, the effect of doping concentration on the hysteresis window is minimal, particularly with thick FE layer. Our model provides a useful tool to directly investigate hysteresis, which makes it possible to modify the hysteresis window by engineering parameters for different target applications.