Understanding and Variability of Lateral Charge Migration in 3D CT-NAND Flash with and Without Band-Gap Engineered Barriers

3D NAND Flash represents the unmatchable non- volatile memory concerning the bit-cost scaling efficiency and a role model for all emerging memories. Yet some reliability features of these devices i.e. quantification of the threshold voltage shift due to the lateral and vertical migration/loss of charges (LCL and VCL, respectively) is not fully understood. In this study we use a multi-scale modeling approach start from identification of the defects responsible for the charge trapping and quantify the LCL and VLC. As a part of engineering of the barrier we investigate also band-gap engineered (BGE) devices. We show that LCL dominates the charge loss during the retention and that highest portion of injected charge ends up in Al
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layer of BGE device.