Reliability Analysis of a Delay-Locked Loop Under HCI and BTI Degradation

This paper studies the impact of hot carrier injection and bias temperature instability on a mixed-signal delay locked loop, at the block and system levels. Aging affects delays on the reset line of the phase detector, degrading sensitivity to input phase differences. Aging also increases threshold voltage mismatch in the charge pump, causing the control voltage of the voltage-controlled delay line to drift, reducing the acquisition time. The delay range of the voltage-controlled delay line also shifts due to aging. Numerical results on a 45nm CMOS process are presented.