Linear Processor Array Architectures for Similarity Distance Computation

Processor array architectures have been employed, as an accelerator, to compute similarity distance found in a variety of data mining algorithms. However, most of the proposed architectures in existing literature are designed in an ad hoc manner. Furthermore, data dependencies have not been analyzed and often only one design choice is considered for the scheduling and mapping of computational tasks. In this work, we present a systematic technique to design linear processor arrays for the computation of similarity distance matrices. The technique employed is used to define the computation domain of the algorithm, with time restrictions on input and output variables. Six scheduling vectors and their associated projection matrices are generated to illustrate our systematic technique. The six possible design options obtained are analyzed in terms of area and time complexities. We are also able to derive a previously existing processor array in the literature by modifying the scheduling vector for one of the proposed architectures. Field Programmable Gate Array (FPGA) Implementations show that our proposed architecture achieves better performance in both speed and area.