A Non-Return-to-Zero Charge-Steering Flip-Flop for High-Speed Wireline Transceivers

In the recent decade, the demand for circuits that operate at high frequency with low energy has increased. The demand is rushed by big-data and internet-of-things applications. Charge-steering circuits were shown to have superior performance over continuous-time current-steering counterparts. This paper presents a non-return-to-zero charge-steering flip-flop. The proposed flip-flop solves both known issues of charge-steering flip-flops; cascading and inter-symbol interference. Cascading two conventional charge-steering flipflops requires the usage and the presence of in-phase and quadrature clocks. The proposed flip-flop, on the other hand, can be cascaded while using only complementary clocks widening the sampling window for the next flip-flop or comparator. This eliminates the need for generating and distributing in-phase and quadrature clocks which is usually a power-hungry task. The output for the proposed charge-steering flip-flop is valid for the entire cycle enabling potential energy saving. Implement in a 65-nm CMOS technology, the proposed charge-steering flip-flop has the ability to operate at data rates of 30 Gb/s and can thus be used in 60-Gb/s wireline transceivers employing half-rate architectures. The proposed charge steering flip-flop consumes 0.66 mW from a 1-V supply at 30 Gb/s.