Final Electrical Test Process Enhancement for Integrated Circuits

This research was conducted in a manufacturing company producing integrated circuits for global customers. The purpose of this research was to identify ways to reduce invalid defects from the contact open test in the final test process. A cause and effect diagram was used to identify possible causes of problems. After identifying the root causes, they were prioritised by applying the Pareto concept to Failure Mode and Effects Analysis (FMEA) to identify the causes with the most significant impact. The AHP (Analytic Hierarchy Process) method was then used to select the most appropriate machine while Design of Experiment (DOE) was carried out to find the significant factors and optimal parameter settings. In addition, the control plan and standard operating procedure were developed to eliminate other defects. Based on the result, this research was a successful solution for the company since it reduced the defect rates as expected. The results showed significant defect reduction after the improvement process from 2% to 0.5% in Aug 2018. Moreover, the decreasing of scraps in finished goods enabled cost-savings amounting to nearly one million baht per year.