A 28-GHz-band Stacked FET Linear Power Amplifier IC with 36.2 % PAE at 3-dB back-off from P1dB in 56-nm SOI CMOS

This paper presents a high efficiency linear stacked FET power amplifier (PA) IC for 5G wireless communication systems. An adaptive bias circuit is used to enhance linearity and back-off efficiency. In addition, third-order trans-conductance component (g
_m
3) is cancelled by multi-cascode structure. The PA IC is designed, fabricated and fully evaluated in 56-nm SOI CMOS. At a supply voltage of 4 V, the PA IC has exhibited an output power of 20.0 dBm and a PAE of 38.1% at 1-dB gain compression point (P1dB). The PAEs at 3 dB and 6 dB back-off from P1dB are 36.2 % and 28.7 %, respectively. The output IP3 of 25.0 dBm is obtained.