Output Response Analyzer of Built-in-Self-Test for 14-Bit ADC in 0.13µm CMOS Technology

This paper presents a design of an output response analyzer (ORA) for a built-in-self-test (BIST) implemented in 0.13μm logic CMOS technology. It evaluates the differential nonlinearity, integral nonlinearity, offset and gain error of a 14-bit analog to digital converter. A Verilog hardware description language (HDL) code was created to define the behavioral description of the design which adheres to the specifications. Analyses were performed to determine the cell area and the timing (at 10ns clock period) and power-related properties of the design. Results show that the design occupies 4895.45mm²of cell area, which represent 0.15% to 2.45% of area overhead over typical 14-bit Analog to Digital Converters (ADCs). The timing analyses show that the setup and hold time are 7.07ns and 0.38ns, respectively, which imply that there is no timing issue for a clock period of as low as 10ns. The power characteristics of the ORA show that the total dynamic power of the design equals 72.0937μW.