Optimum Design and FPGA Implementation of Fractional Order Digital Integrator

The aim of this paper is to design fractional order digital integrator and implement it on FPGA. Optimized coefficients of second order infinite impulse response system is determined using nature inspired Ant Lion Optimization algorithm such that the frequency response of IIR based FODI becomes equivalent to the ideal frequency response of FODI. Comparison of the proposed IIR-FODI with the existing literature in terms of frequency magnitude response, absolute magnitude error and root mean square magnitude error is reported. Transposed direct form II architecture is used to realize the design on Xilinx Virtex-7 FPGA through system generator for DSP design tool. Post implementation, input output waveforms, resource utilization and critical path delay for fixed point and floating point data representation is presented.