Design of CMOS Based D Flip-Flop with Different Low Power Techniques

This paper shows designs of CMOS based D flip flop circuits using the forced nMOS stacking, LCNT (leakage controlled nMOS transistor), and LECTOR (leakage controlled transistor). Flip-Flops are the critical foundation stones of all modern digital circuits. This paper reports design and analysis of various low power techniques. The simulations have been carried out in SPICE based on TSMC 180nm CMOS technology. Conventional D flip-flop using the primary CMOS inverters is used as a reference circuit. A comparison based on power consumption, propagation time delay, and PDP is carried out. The conventional design shows the power dissipation of 470.811pW with a supply of 1.8V. The LCNT and LECTOR technique shows the power dissipation of 471.216pW and 350.841pW respectively. The proposed forced nMOS stacking technique shows the power dissipation of 149.308pW which gave 68.28% reduction in power consumption as compared to the conventional circuit. The analysis gives us a deep insight about the performance of the circuit when subjected to different techniques, thereby improving certain aspects of the circuit with a slight trade-off in time delay in few instances.