Demystifying Via Impedance Optimization for High Speed Channels

Signal speeds of high speed channels double almost every generation and with increasing speeds, even a slight impedance discontinuity in the channel can adversely affect signal quality. Channel discontinuities come from several sources and each source must be carefully considered. One common source of channel discontinuity is the signal via. Via impedance needs to be designed with utmost care because high speed channels inevitably encounter a lot of via transitions in the form of BGA breakout vias, AC coupling capacitor vias, connector vias and transition vias. Upfront modeling and analysis for vias can mitigate reflections in a layout to achieve the required performance. In this paper, a method to optimize vias in both time and frequency domains is explained. A lot of common mistakes made in terms of rise-time assumptions, reference impedances and impedance targets are demystified and explained in detail with examples. This paper highlights the impact on via impedance on high frequency designs and showcases how in correct modeling assumptions can lead to suboptimal designs or in unnecessary overdesigning of the channels.