Graph-Grammar-Based Analog Circuit Topology Synthesis

Automatically constructing analog circuit topology according to specifications is always a challenging task, due to the high complexity and substantial design expertise required. This paper proposes a graph-grammar-based method that can efficiently and automatically generate analog circuit topologies, which can be applied to general analog circuit synthesis frameworks for analog circuit design. The topology generation process is encoded by constructing a binary tree, in which the leaf nodes are decomposed according to a set of grammar rules. In order to guarantee only unique circuit structures to be generated, double isomorphism checks are applied at both tree structure level and circuit transistor level. Our experimental results demonstrate the high efficiency and wide applicability of the proposed method.