Design Space Exploration of Ovonic Threshold Switch (OTS) for Sub-Threshold Read Operation in Cross-Point Memory Arrays

We perform SPICE based simulations to identify the possibility and challenges of a sub-threshold read operation in a cross-point one-selector and one-resistive memory (1S-1R) array enabled by an ovonic threshold switch (OTS) with a high threshold voltage (Vth) and strong non-linearity of a sub-threshold regime. Here, it is important to read an on/off ratio below the Vth, where the OTS has not yet been turned on, leading to robust reliability characteristics of the 1S-1R. We show that the on/off ratio can be observed by adjusting the resistance range of the memory close to the threshold resistance of the OTS. Then, increasing the non-linearity in the sub-threshold regime of the OTS improves the on/off ratio. However, reading the obtained on/off ratio even in very small array is difficult due to sneak-path currents. Therefore, a low off-current of the OTS should be lower than 0.1 nA at 1 V to ensure a minimum readable on/off ratio (~2 ×) in the array.