A Two-Stage Push-Pull Power Amplifier with Electro-Thermal Effects Study in 130 nm SOI CMOS for IEEE 802.11ac Applications

The paper presents a two-stage cascade push-pull power amplifier (PA) with floating-body transistors in 130 nm Silicon-On-Insulator (SOI) CMOS process for IEEE 802.11ac application. In the proposed design, on chip baluns, which can realize impedance matching, are used in driver stage amplifier input and power stage amplifier output matching networks. The proposed PA can achieve high gain, high output power and wide bandwidth at the same time with 0.819mm² chip area including pads. With 2.5 V supply voltage, the implemented PA achieves 20.31 dB power gain with 3 dB bandwidth range from 3.9 GHz to 6.19 GHz, 20.96 dBm output power at 1 dB compression point (OP-1dB) and 9.85% power added efficiency (PAE).