A Noise and Spur Reduction Technique for ΔΣ Fractional-N Bang-Bang PLLs with Embedded Phase Domain Filtering

This paper presents an effective way of noise and spur reduction in the design of ΔΣ fractional-N bang-bang phase-locked loops (BBPLLs). An integer-N BBPLL based phase domain low pass filter (PDLPF) significantly suppresses the high frequency quantization noise of the ΔΣ modulator in the feedback path, which mitigates phase folding effects of the bang-bang phase detector (BBPD). A ΔΣ fractional-N BBPLL, combined with the PDLPF for deterministic jitter (DJ) reduction, is implemented in 65nm CMOS. Simulation results show that the proposed architecture achieves an in-band noise reduction of 27dB and a spur reduction of 23dB at 5GHz output with the PDLPF enabled.