A Ka-Band Stacked Power Amplifier with 24.8-dBm Output Power and 24.3% PAE in 65-nm CMOS Technology

This paper presents a fully integrated one-stage three-stack Ka-band power amplifier (PA) with neutralization technique in 65-nm CMOS process for 5G applications. A transformer-based power combiner is adopted to combine two differential PA cells to increase the output power. Four small size stacked sets are combined together as one differential PA cell for increasing efficiency. A shunt feedback drain-source capacitor is utilized to divide the output voltage equally between drain and source of each individual transistor in three-stack PA. The proposed PA achieves the measured saturated output power (P
_sat
) of 24.8 dBm with 24.3% peak power added efficiency (PAE), output 1-dB compression point (OP
_1dB
) of 21.7 dBm and 17.5-dB power gain at 38 GHz. The chip size without pads is 0.146 mm
²
. To the author's best knowledge, this stacked PA demonstrates the best power performance compared with the reported CMOS PAs around 38 GHz.