Gate triggering: a new framework for minimizing glitch power dissipation in static CMOS ICs and its ILP-based optimization

Glitches are an important source of power dissipation in static CMOS ICs that can contribute to as much as 70% of total power dissipation in certain cases (e.g., arithmetic modules). Although research into various aspects of glitch power dissipation has been undertaken in the past, most approaches to addressing it are ad hoc and limited in their applicability. In this paper, we propose a new framework, gate triggering, for systematically minimizing glitch power dissipation in static CMOSICs. The framework is based on the idea that glitches can be effectively minimized by triggering logic evaluation at a gate only when all of its inputs have stabilized. For this purpose, to every potentially glitchy gate is added a small amount of control logic, which, when enabled, triggers logic evaluation at the gate. A clocked delay chain is employed to generate enable signals at the proper times for all gates to be triggered. We present an integer linear programming (ILP) formulation to minimize the overheads (viz. delay element, control logic, and extra wiring) of our approach subject to a critical-path delay constraint. Application of the new approach to test circuits (such as ripple carry adder and array multiplier) in 1.2 /spl mu/ technology yields 95% or more elimination of glitch power dissipation with negligible area and timing overheads after optimization. An added advantage of the approach is that short-circuit power dissipation at all triggered gates is also minimized-short-circuit power dissipation in current standard-cell based designs can exceed 50% of the total power dissipation.