Low Latency Semi-iterative CORDIC Algorithm using Normalized Angle Recoding and its VLSI Implementation

In this article, we have proposed a semi-iterative 2D Co-ordinate Rotation Digital Computer (CORDIC) algorithm and presented the VLSI architecture of it. Our proposed CORDIC algorithm is based on our own Normalized Angle Recoding based Hybrid (NARH) method. The proposed algorithm and its corresponding architecture are innovative and unique, because our proposed CORDIC is not fully iterative unlike all other CORDIC algorithms. The latency of our proposed CORDIC is the least in comparison to most of the other significant and latest CORDIC algorithms. We have also judiciously parallelized the computation of the scale factor. The proposed high speed CORDIC algorithm has been realized in Field Programmable Gate Array(FPGA). Though the VLSI architecture of the proposed algorithm is prototyped using 16 bit fixed point format, it can easily be extended for higher bit length. The performance of the proposed VLSI architecture has extensively been assessed based on various performance metrics like latency, hardware complexities, maximum operating frequency and power requirement. Our proposed prototype architecture of NARH based proposed CORDIC algorithm outshines most of the notable CORDIC architectures in respect of the above mentioned performance parameters.