Low Latency Max Log MAP based Turbo Decoder

The framework of convolutional coding persisting today incorporates decoder designs whose performance varies with the underlying algorithm's efficiency. Traditional decoder design methodology started from Viterbi's algorithm, and is currently trending towards different implementations of MAP algorithm. As process and technology advances from the basic fixed point multiplier to the present Booth multiplier, the decoding performance varies. Optimization of decoder's performance and hence its reliability can be enhanced by the implementation of more systematic and efficient underlying multipliers. This paper focuses on bringing out the performance variations of a Max log MAP algorithm based turbo decoder on implemented with fixed point, Vedic and Booth multipliers.