Development of Fault Diagnosis System Using Fault Injection for Discrete Architectures

Physical realization of momentous electronic circuit elements have becomes possible due to the avant-garde integration technology. Such components are propitiously providing high speed data execution with least power utilization in highly optimized area. With such attainment, fault diagnosis becomes significant in order to provide reliable product to the end user. The present research work introduces a methodology to evaluate the testability of the digital circuit. In the proposed work, the architecture is developed which produces expected output combinations and output combinations which are possible when fault condition occurs in the circuit. The architecture is implemented using VLSI-FPGA architecture, famous for implementing concurrent architecture and is targeted to Virtex FPGA for best optimization.