Experimental Quantification of Hardware Requirements for FPGA-Based Reconfigurable PMUs

Phasor Measurement Units (PMUs) are becoming intrinsic components of modern power systems. The synchrophasor estimation algorithms in PMUs pose stringent computational demands, which makes the application of Field Programmable Gate Arrays (FPGA) highly attractive. Previous works reported the implementation of PMU algorithms on specific FPGA-targets using a particular PMU design. This paper explores the implementation of different PMU designs on multiple FPGA targets using Xilinx and NI software and hardware infrastructures and toolsets. In this process, a metric has been formulated to predict FPGA-target hardware requirements. The metric allows predicting if an FPGA-target meets the needs to deploy a given PMU design resulting in significant engineering design time savings. Since the compilation/synthesis on FPGAs is a time-consuming job, this metric can reduce the implementation time for FPGA-based PMUs drastically and can help in determining if additional functionalities can be added.