Reliability Analysis of On-Chip Wireless Links for Many Core WNoCs

On-chip wireless interconnects in Wireless Network-on-Chip (WNoC) show considerable promise for significantly improving communication performance and energy in many core processors. Wireless links offer high bandwidth, low latency and low per bit energy consumption, along with broadcast capability. While, they offer several advantages, wireless links are inherently unreliable, unlike wired links. Wireless transmission in on-chip network faces challenges from complex channel characteristics, channel sharing and allocation, choice of modulation, noise in analog circuits and channel, etc. Unlike traditional wireless communication that generally uses error correction and data retransmission techniques to improve reliability, on-chip wireless network suffers from high performance and power overheads in using such techniques. This paper explores the challenges for reliable wireless transmission in WNoCs, especially the impact of wireless channel and choice of modulation schemes. The complex nature of on-chip wireless channel adds adverse effects like high path loss, dispersion, etc. along with noise in channel. This results in packet loss/errors or performance and energy degradation. While modulation schemes like OOK are susceptible to these channel effects, techniques like OFDM, CDMA are robust against such effects but add power/area overheads. Using these analyses, we propose techniques to improve wireless link reliability, while not adding high performance and energy overheads. The proposed improvements are evaluated for reliability using MATLAB modeling of the wireless communication and for network performance and energy.