Smoothing the Way for Digital Phase-Locked Loops: Clock Generation in the Future with Digital Signal Processing for Mitigating Spur and Interference

Phase-locked loops (PLLs) are widely deployed in most electronic systems to generate a desired clock frequency, perform clock data recovery (CDR), and achieve frequency or phase modulation depending on the intended applications, such as Wi-Fi, Bluetooth, 5G, gigabit Ethernet, or optical fiber communication. Recently, the trend toward system-on-chip (SoC) has resulted in the need for a low-cost, robust, and highly reconfigurable PLL architecture [1], [3]?[8], [11], [13]?[22], [28]?[30], [32], [35]. This large-scale integration for advanced application requires a deeply scaled, integrated circuit technology with a low supply voltage, but it inevitably results in a design bottleneck, such as voltage headroom or reliability issues, for analog PLLs. Hence, interest in a digital PLL (DPLL) architecture has increased as its digital nature offers the advantage of technology scaling in a way that analog PLLs do not. In addition, the DPLL architecture is more flexible and reduces area and power consumption because its compact digital logics replace bulky and passive analog components.