A Methodology for distributed Co-design and Coextraction of Die Re-distribution Layer and Package

A complete methodology for distributed co-design and co-analysis of Die Re-distribution layer with the package is developed and presented. A test chip is designed in a generic 65nm process with six metal layers out of which 3 layers of RDL have been exported to a Package design tool and placed on top of a four-layer flip-chip package. After successfully co-designing the RDL routes and bumps in conjunction with package routes, the three RDL layers were exported back to the IC design environment for final sanity checks. An S-parameter extraction on the combined geometry including RDL layers and Package layers is then carried out in an EM solver. It is shown that combined geometry s-parameter extraction on signal net was able to capture the resonance due to RDL and Package layer coupling at 1.9GHz as compared to when extraction was carried out only on Package geometry.