Design of Adiabatic Quantum-Flux-Parametron Register Files Using a Top-Down Design Flow

Offering extremely high energy-efficiency, the adiabatic quantum-flux-parametron (AQFP) logic family is considered a promising candidate as a future low-power technology for building high-performance computing systems. In this paper, we provide the design of M-word × N-bit dual-port register files as an essential component of an AQFP microprocessor. This design consists of one decoder for data writing, two multiplexers for read out, and an array of registers as storage elements. In order to reduce the design difficulties and improve the design robustness, we employed a top-down AQFP very-large-scale integration (VLSI) design flow to implement this register file. The proposed design flow is composed of high-level synthesis, a specialized AQFP interpreter, a genetic-algorithm-based routing approach, and hardware-description-language-based back-end verification. As a case study, we designed and fabricated an 8-to-1 4-bit multiplexer used as the component circuit of the designed register file. In low-speed test, we confirmed the correct operations across all channels of the multiplexer.