Timer Based Digital Implementation of Advanced Bus-Clamping PWM Techniques

Advanced bus-clamping pulse width modulation (ABCPWM) techniques have been shown to outperform continuous and discontinuous (i.e. bus-clamping) pulse width modulation methods in terms of line current distortion, pulsating torque (in case of motor drives) and inverter switching loss at a given average switching frequency under certain operating conditions. These ABCPWM methods clamp a phase to a dc rail (as in discontinuous modulation) and switch another phase at twice the nominal switching frequency (unlike discontinuous modulation). The `double-switching' of the three phases in different intervals makes the implementation of such modulation schemes challenging. Further, the microcontrollers and digital signal processors available for power electronic applications are oriented towards implementation of continuous and discontinuous modulation schemes. This paper discusses the implementation of ABCPWM schemes on such processors. The features of the on-chip pulse-generation module in the digital signal processor are effectively utilized so as to avoid external hardware and to reduce the number of interrupts.