Data Bandwidth Reduction in Deep Neural Network SoCs using History Buffer and Huffman Coding

Convolutional neural networks deliver state of the art accuracy in classification and detection of objects which are of interest for many consumer and automotive applications. However, they require significant memory bandwidth and storage for intermediate computations apart from huge computing resources. There is an important requirement to reduce the bandwidth and memory for the cost and yield reasons. Here, a method and circuit is discussed to reduce the memory bandwidth for intermediate results.