Performance Enhancement of Multi-Gate MOSFETs Using Gate Dielectric Engineering

Short channel effects (SCEs) are major roadblocks for Bulk MOSFETs to scale down into nanometer regime. Multi-gate (Double-Gate (DG), Triple-gate (TG) Gate all around (GAA)) structures are the best alternatives to tackle the SCEs. This paper initially compares multi-gate devices along with single gate with respect to different gate oxide thickness. To improve the performance of these devices, gate-stack (stacking of SiO₂ and HfO₂ layers) configuration is introduced and compared their electrical characteristics such as ION/IOFF ratio, Subthreshold swing, and drain induced barrier lowering (DIBL). Further, gate-engineered dielectric layer comprising of one dielectric (HfO₂) in half-gate length and another dielectric (SiO₂) in the other half of gate length are used side by side with identical thickness. At all stages, GAA structure exhibits better performance over the others. In order to estimate the devices performances at circuit level, a resistive load based inverter circuit has been simulated with gate-engineered multi-gate structures and found that GAA based inverter gives less delay time in comparison with others.