Single event transients in deep submicron CMOS

Single event transients (SET) occur when an energetic subatomic particle strikes a combinational logic element. The charge deposited by the particle causes a transient voltage disturbance, which can propagate to a storage element and be latched, resulting in single event upset (SEU). The logic design style, storage element behavior, and system timing requirements greatly impact the probability that an SET will cause an SEU. These effects are explored through circuit simulations and heavy ion testing of prototype devices.