Performance Analysis of TFET Using Si0.35Ge0.65/Si Hetero-junction Hetero-dielectric with Buried Oxide Layer

Limitations of MOSFET due to device scaling can be overcome by Tunnel FET that works on Band-to-Band tunneling phenomenon, have sub-threshold swing less than 60mV/dec, low OFF-state leakage current and operate at low voltages. However ITRS requirement of high ON current which is compatible with current MOSFET based circuits is not supported by TFET. The low ON current of TFET can be improved using different structure, channel material, gate oxide material and appropriate gate work-function. In this paper we have designed and simulated a SiGe/Si hetero-junction n-Tunnel FET. SiGe is used as source material and HfO₂/SiO₂ hetero-dielectric is used as gate oxide material. The simulation is done in licensed Cogenda TCAD version 1.7.4. The proposed device is compared with homo-junction TFET structure with Si, Ge and SiGe as thin film body material and also with different hetero-junction TFET by changing source material to Ge. The ON current, OFF current, Sub-threshold slope, switching delay, power dissipation and PDP of these devices are compared. With the proposed device a higher ON current of 1.2763mA/μm, Sub-threshold slope of 40.4mv/dec and ION/IOFF ratio of 1.2×10¹¹ is obtained when compared with other TFET structures. Thus the investigated device could prove to be an upcoming alternative to be used for high speed and low power FPGA application.