Design Implementation of 10T Static Random Access Memory Cell Using Stacked Transistors for Power Dissipation Reduction

This SRAM cell is composed of combination of normal transistors and high voltage threshold transistors (sleep transistors) and can store one bit of data. Moreover, the designed SRAM architecture is composed of 4x16 decoders, pre-charge circuit, write or read selector circuit, sense amplifier circuit, write driver circuit, bank selector, column selector and SRAM cell arrays. The modified SRAM reduces the power dissipation by using sleep transistor stacking technique in a basic SRAM cell. Moreover, the designed SRAM memory is also partitioned into four banks, which contain 2048 SRAM cells each and implemented in a 128x64-cell array. The overall design has an average power of 7.71mW and the overall results performance were compared to the conventional 6T SRAM architecture. Both the modified and conventional SRAM architectures have the same design blocks except the SRAM cell. The operating voltage and frequency used in this design is 1.2V and 500 MHz, respectively. In addition, the modified SRAM in this paper has 8192 bits of memory capacity and implemented in TSMC 65nm CMOS Technology.