24.2 A 7nm 2.1GHz Dual-Port SRAM with WL-RC Optimization and Dummy-Read-Recovery Circuitry to Mitigate Read- Disturb-Write Issue

Continued transistor scaling increases random $V_{t}$ variation, and wire routing resistance and capacitance; it degrades SRAM performance and results in SRAM design difficulties. Although dual-port (DP) SRAM is useful, because it can offer simultaneous read and write operations with two asynchronous clocks, circuit design is more complex than for a single-port (SP) SRAM when considering worst-case operation. In particular, WL resistance and capacitance (RC) degradation caused by process scaling and read-disturb-write (RDW) problem in a DP-SRAM bitcell are major challenges for DP-SRAM design in advanced technology nodes.