A Power Hardware-In-the-Loop Scheme for Load Emulation Applications

Technological innovations in electrical systems require the development of testing and validation tools that provide a safe environment and allow configuring different operating conditions. In this regard, power hardware-in-the-loop (PHIL) simulation is a suitable tool that interacts with physical components knowing as hardware under test (HuT) according to a mathematical model. In this work, a PHIL simulation for both electrical source analysis and load studies as HuT using linear and nonlinear loads is carried out. It is performed by means of an ideal transformer model (ITM) as interface algorithm along with a feedback stage using digital filtering, where a state-space control is simulated and implemented in a real-time hardware and a voltage source inverter (VSI) is used as a power amplifier. Different loads are used to validate the PHIL implementation such as resistive load, resistive-inductive load, and a nonlinear load by considering a dc motor. In this work, two HuT are used, a transformer arrangement and a power inverter.