Design and FPGA Implementation of Residual Data in HEVC CABAC Encoder

Context-based Adaptive Binary Arithmetic Coding (CABAC) is an efficient entropy codec, adopted by H.264/AVC (advanced video codec) and H.265/HEVC (High Efficiency Video Coding) standards. HEVC is the newest standard of video compression, it is expected to achieve at a least 4K and 8K ultra-HD resolution up to 120 fps. CABAC is already a well-known bottleneck in H.265. In this paper, we propose a new RTL (Register Transfer Level) architecture of HEVC CABAC encoder, where all Syntax Elements (SE) transmitted for 4 x 4 sub-block are studied and implemented. This architecture is described using structural hardware description VHDL language. To achieve a good compromise in terms of path-delay, speed and hardware resources some optimization techniques are adopted. Our implementation of the HEVC CABAC encoder processed for 1.2 bins/cycle needs only 478 of slices with a maximum frequency of 134.885 MHz and high throughput of 161.86 Mbin/s. Simulation and hardware implementation on Xilinx FPGA technology results demonstrates that the proposed architecture provides a good compromise in terms of resources and throughput.