FPGA Hardware Design of a Unified Chaotic System for CTRNG

This paper, proposes a digital implementation of unified chaotic system using hardware approach. This approach is based on structural parallel and pipelined hardware description using VHDL. Experimental results on Xilinx FPGA Zybo board demonstrates that we can get different chaotic systems namely Lorenz, Chen and Lu by controlling the parameter α manually by an external switch or automatically by a multiplexer with a chaotic selection. Generated chaotic sequences are then used to design Chaotic True Random Number Generator (CTRNG) which is can be used in many real secure embedded applications.