Hybrid Latch-Type Offset Tolerant Sense Amplifier for Low-Voltage SRAMs

Sense amplifier (SA) input-referred offset often dictates the minimum required differential input ($\Delta V_{\textrm {BL-min}}$ ) and is an important factor in realizing low-voltage static random access memories. This paper presents a HYbrid latch-type Sense Amplifier (HYSA-QZ), where the bitline signals are supplied to multiple internal nodes to significantly reduce $\Delta V_{\textrm {BL-min}}$ . A 65-nm CMOS test chip with arrays of the HYSA-QZ, two intermediate formulations of the HYSA-QZ, conventional current latch SA (CLSA), and conventional voltage latch SA (VLSA) were fabricated. Measurements over 5120 SAs of each type show that the HYSA-QZ implemented with regular-$V_{\mathrm{ T}}$ transistors require 50.0%, and 22.8% lower $\Delta \text{V}_{\textrm {BL-min}}$ with 6.5% (or 4.5%) and 30.7% (or 18.8%) of total gate (or layout) area overhead compared to CLSA and VLSA at 0.4 V, respectively. Iso-gate-area offset improvement was substantiated with Pelgrom's mismatch model, where the HYSA-QZ with regular-${\mathrm{ V}}_{\mathrm{ T}}$ transistors showed 46.6% and 7.7% improvements in measured standard deviation of offset distribution compared with CLSA and VLSA, respectively. Measured $\Delta V_{\textrm {BL-min}}$ for the HYSA-QZ remains stable and low over a temperature range from 0 °C to 75 °C at 0.4 V. Moreover, an additional 13.0% reduction in $\Delta V_{\textrm {BL-min}}$ was measured in the HYSA-QZ when using low-$V_{\mathrm{ T}}$ transistors. Finally, the HYSA-QZ operates reliably at $V_{\textrm {DD-min}}$ of 260 mV in 25 °C.