Resynthesis for FPGA During Technology Mapping Stage

Now the problem of digital circuits synthesis is relevant for design flows for FPGAs due to area and traceability limits. This leads to the need to develop such methods and algorithms that allow to obtaining an optimal circuit representation based on lookup tables optimized for regular structure of target device. In this article we propose resynthesis algorithm for digital circuits during technology mapping stage for FPGA design flow. It based on intergate resynthesis algorithm at transistor level that uses the SP-graph for a logical function representation and Boolean transformations.