Research of Reconstructed Wafer Surface Planarity on the Metall-Compound-Silicon Boundary for Multi-Chip Module with Embedded Dies

One of the most important problem for multi-chip module manufacturing technology with embedded in carrier cavities dies is ensuring surface planarity. Critical areas in this case are the gaps between the carrier and dies, filled with compound. Absence of planar surface in these areas can lead to defects in commutation layers, internal stresses and, as result, to significant decrease in assembly reliability. In this article, surface reliefs of carrier with embedded dies after molding with variety epoxy and silicone based polymers have been investigated. As a result, the minimum irregularity height of about 4 microns was achieved for optimal combination of molding compound and polyimide coating in the minimum gap with of about 250 microns.