Robust WLCSPs: Enabling 5-Side Protection

The demand for Wafer Level Chip Scale Packages (WLCSP) has experienced strong growth (∼10% CAGR 2017-2021) due to the surge in demand for a thinner and smaller form factor in advanced mobile and wearable products. Although WLCSP is now a widely accepted package solution, the initial acceptance was limited due to concerns with the SMT (Surface Mount Technology) assembly process and the fragile nature of the exposed silicon inherent in the package design. While assembly skills and methods have improved since the introduction of WLCSP, damage to the exposed silicon remains a concern. This is particularly true for advanced node products with fragile dielectric layers. Handling defects such as die corner stress, chipping and or die cracks can cause functional failures which may happen during the WLCSP processing or arise over the electronic product’s life due to environmental, temperature or mechanic use stresses.This paper introduces two WLCSP solutions, with 5-side protection, eWLCSP (encapsulated WLCSP) and FI-ECP (Fan In Encapsulated Chip Package). These two different technologies have a thin protective coating applied to all exposed silicon surfaces on the die. The applied coating (resin or plastics) protects the silicon and fragile dielectrics and prevents handling damage during dicing and assembly operations, effectively providing a durable packaged part in the form factor of a WLCSP. The manufacturing process leverages on existing high volume manufacturing methods with exceptionally high process yields.eWLCSP follows eWLB (embedded Wafer Level Ball Grid Array) process flow which has been proven in high volume production for the last 10 years in the industry. FI-ECP has a unique process flow with thin die and film lamination process for 5-side protection. It can use plasma dicing or dicing with a reconstitution process, depending on the saw street design.