LVCMOS Based Energy Efficient D flip-flop Design

In this paper, a d flip=flop is designed using Xilinx ISE design suite 14.2. The language used is Verilog. The flip flop designed is FPGA based and will be dissipating the minimum amount of power. The I/O standard used here is LVCMOS (Low Voltage Complementary Metal Oxide Semiconductor) which will help us in achieving the goal of minimum power dissipation. The analysis is done on different families like Artix-7, Spartan-3, Spartan-6, Virtex-6, and Virtex-5. The scaling is done on frequency and the frequencies used are 1 Ghz, 2 Ghz, 3 Ghz, 4 Ghz and 5 Ghz.