Performance Evaluation of Frame-level Parallelization in HEVC Intra Coding Using Heterogeneous Multicore Platforms

High Efficiency Video Coding (HEVC) is the latest video coding standard released as a successor of H.264/AVC, it expected to reduce the bitrate by 50% for the same perceptual quality. One of the major contributors to the higher compression performance of HEVC is the introduction of larger Coding Units (CU) with recursive partitioning mechanisms. This achievement in performance is accompanied by a high computational complexity, making this new standard very difficult to be embedded in current multimedia services and broadcast platforms. In this paper, a performance evaluation of All-Intra (AI) parallel realization of HEVC encoder is proposed, using a heterogeneous Octa-core CubieBoard4 platform that includes two quad-core ARM A7 and ARM A15. We used the OpenMP paradigm for parallel realization where each thread is assigned to a core processor to encode a separate frame. AI configuration is used to break coding dependencies between successive frames, which allow the parallel processing of a set of images. Experimental results shows that the proposed parallel realization of HEVC encoder, using eight threads, reduces the computational complexity to about 4.35×, without any loss in coding performance. These results do not match to the expected acceleration due to the heterogeneity of the platform.