Multiple Bypass Bins FPGA Implementation of H.256 CABAC Encoder

Actually, the HEVC (High Efficiency Video Coding) is becoming the most important consumer application platforms. Compared with its predecessor AVC (advanced video codec) standard, it can support the UHD (Ultra High Definition) picture at 120 fps. H.265 adopts many advanced techniques such as SAO (Sample Adaptive Offset) filter, intra and inter prediction and CABAC entropy coding. CABAC (Context-based adaptive binary arithmetic coding) is adopted by AVC and HEVC standards. In H.265 CABAC, the bypassed syntax elements have direct impact on the total bite rate. This point is verified, estimated and simulated in our work at the small unit level on MATLAB software. Moreover, we propose hardware design of multiple bypass bins H.265 CABAC encoder. This architecture is implemented on different FPGA devices. The synthesis results demonstrate that our proposed architecture can process 1 to 5 bypass bins per cycle to ensure a good compromise between the throughput and the hardware cost.