Sinusoid Based Foreground Calibration Algorithm of a Pipeline ADC Using Time Averaged Radix Extraction

The paper presents a novel digital foreground calibration algorithm of a pipeline ADC. Unlike many of the contemporary digital calibration algorithms, which use least mean square (LMS) based iterative method of radix extraction, the proposed algorithm extracts the radix using a simple time-average determination of the radices. In this paper a 10-bit pipeline ADC has been implemented with two non-ideal 1.5-bit MSB stages. The back-end ADC (BE-ADC) contains 6 1.5-bit stages followed by a 2-bit flash stage. Since the radices of the first two stages equate to their multiplying-digital-to-analog-converter (MDAC) gains, determination of the radices helps to linearize the ADC output. Although the proposed calibration algorithm is capable of extracting the radices of all the stages, as an illustration only two stage calibration process has been presented in this paper. Simulation results of a 10-bit pipeline ADC sampling an input signal at approximately Nyquist rate show before calibration the ADC produces a signal-to-noise-and-distortion-ratio (SNDR) of 35.42 dB and spurious-free-dynamic-range (SFDR) of 42.16 dB. After applying the calibration, SNDR and SFDR improves to 56.89 dB and 61.37 dB respectively.