Low Power Scan Chain Architecture Based on Circuit Topology

Scan-based test is widely used method to test the digital circuits, increasing the controllability of the circuit under test. However high controllability can cause fatal problems by excessive test power consumption. To resolve these problem, this paper proposes a scan chain architecture which reduces the test power consumption. The proposed method decreases the test data volume by partitioning a scan chain into many scan segments. The scan chain partitioning is performed based on circuit topology, and it increases the number of scan segments that can be bypassed. Simulation results show that the proposed method reduces the test power consumption up to 43.33% compared to the previous work.