Dynamic voltage Drop induced Path Delay Analysis for STV and NTV Circuits during At-speed Scan Test

The NTV circuit has been introduced as a new low power design concept, which increases energy efficiency significantly. However, delay sensitivity of the NTV circuit is a major challenge. In addition, this problem can be more critical during at-speed scan test because of the dynamic voltage drop issue. In this paper, we propose a comparison of dynamic voltage drop induced path delay between STV and NTV circuits during at-speed scan test. To the best knowledge of the authors, it is the first time to analyze the voltage drop induced path delay during the NTV circuit scan test. Experimental results show that the path delay increment of NTV is larger than that of STV although the dynamic voltage drop of NTV is smaller than that of STV.